ATS'17

Program (Advanced Program PDF version)

2017 ATS Program At A Glance


11/27 Mon. 11/28 Tues.
11/29 Wed.
11/30 Thur.
09:00~10:20
Tutorial 1
Power-Aware Testing
in the Era of IoT
09:00~10:30
Opening
Keynote #1
08:30~10:10
Keynote #2
Keynote #3
08:30~09:45
Sessions 4A/4B/4C
10:20~10:40
Coffee Break
10:30~11:00
Coffee Break
10:10~10:40
Coffee Break
09:45~10:15
Coffee Break
10:40~12:00
Tutorial 1
Power-Aware Testing
in the Era of IoT
11:00~11:50
Invited Talk
10:40~12:20
Sessions 3A/3B/3C
10:15~11:30
Sessions 5A/5B/5C
12:00~13:30
Lunch
11:50~13:00
Lunch
12:20~13:30
Lunch
( GSC Hiroshima
High School Student
Research Poster Presentation
)

13:30~14:50
Tutorial 2
Data-Driven
Resiliency Solutions
for Integrated
Circuits and Systems
13:00~14:15
Sessions 1A/1B/1C
13:30~17:00
Social Event
WRTLT
14:50~15:10
Coffee Break
14:15~14:45
Coffee Break
15:10~16:30
Tutorial 2
Data-Driven
Resiliency Solutions
for Integrated
Circuits and Systems
14:45~16:25
Sessions 2A/2B/2C
18:00~20:00
Welcome Reception
17:30~21:00
Banquet


Technical Program

    November, 27th
    ----------------------------------------------------------------------------------------------------
    Registration
    Time: 08:00-09:00



    Tutorial #1 – Power-Aware Testing in the Era of IoT
    Room: Grand Hall A
    Time: 09:00-12:00
    Presenter #1: Xiaoqing Wen (Kyushu Institute of Technology)
    Presenter #2: Patrick Girard (LIRMM / CNRS)


    Lunch Break
    Time: 12:00-13:30


    Tutorial #2 – Data-Driven Resiliency Solutions for Integrated Circuits and Systems
    Room: Grand Hall A
    Time: 13:30~16:30
    Presenter: Krishnendu Chakrabarty (Duke University)


    Welcome Reception
    Time: 18:00-20:00



    November, 28th
    ------------------------------------------------------------------------------------------------------
    Registration
    Time: 08:00-09:00


    Plenary Session
    Room: Grand Hall
    Time: 09:00-11:50
    • Welcome Message
    Jiun-Lang Huang (National Taiwan University), General Chair
    • Program Introduction
    Jin-Fu Li (National Central University), Program Chair
    • Keynote #1: The Revival of BIST: From Self-Test to Self-Healing
    Presenter: Hans-Joachim Wunderlich (University of Stuttgart)
    Chair: Kuen-Jong Lee (National Cheng Kong University)
    • 10:30-11:00 Break
    • Invited Talk: A Foundry’s View of Hardware Security
    Presenter: Shih-Lien Lu (TSMC)
    Chair: Jiun-Lang Huang (National Taiwan University)


    Lunch Break
    Room: Grand Hall
    Time: 11:50-13:00


    Session 1A: PhD Thesis Award Contest
    Room: Grand Hall A
    Time: 13:00-14:15
    Organizer: Hiroshi Takahashi, Ehime University
    Moderator: Hiroshi Takahashi, Ehime University
    1A-1: Trace based design for debug for Post-silicon Validation
    Yun Cheng and Huawei Li (Chinese Academy of Science)

    1A-2: Testing and Synthesis of Reversible Logic Circuit
    Bikromadittya Mondal and Susanta Chakraborty (Indian Institute of Engineering Science and Technology)

    1A-3: Field Test for Ensuring the Functional Safety of Automotive System
    Hanan T. Al-Awadhi and Hiroshi Takahashi (Ehime University)

    1A-4: Power Side-channel Analysis Based Hardware Trojan Detection through Circuit Partitioning
    Fakir Sharif Hossain and Michiko Inoue (NAIST)
    Alex Orailoglu (UCSD)



    Session 1B: Interconnect Test and Measurement
    Room: Grand Hall B
    Time: 13:00-14:15
    Moderator: Katherine Shu-Min Li (National Sun Yat-sen University)
    1B-1: An enhanced boundary scan architecture for inter-die interconnect leakage measurement in 2.5D and 3D packages
    Pok Man Law and Cheng-Wen Wu (National Tsign Hua University)
    Hao-Chiao Hong and Long-Yi Lin (National Chiao Tung University)

    1B-2: On-chip ring oscillator based scheme for TSV delay measurement
    Songwei Pei and Alrashdi Ahmed Rabehb (Beijing University of Chemical Technology)
    Song Jin (North China Electric Power University)

    1B-3: Testing of interconnect defects in memory based reconfigurable logic device (MRLD)
    Senling Wang, Yoshinobu Higami, and Hiroshi Takahashi (Ehime University)
    Masayuki Sato and Mitsunori Katsu (TRL Corp.)
    Shoichi Sekiguchi (Taiyo Yuden)



    Session 1C: Test Compression
    Room: Descartes & Rousseau
    Time: 13:00-14:15
    Moderator: Chun-Lung Hsu (ITRI)
    1C-1: Test pattern compression for probabilistic circuits
    Chih-Ming Chang, Kai-Chieh Yang, James Chien-Mo Li and Hung Chen (National Taiwan University)

    1C-2: Test compression with single-input data spreader and multiple test sessions
    Chang-Wen Chen, Yi-Cheng Kong and Kuen-Jong Lee (National Cheng Kong University)

    1C-3: Test compaction with dynamic updating of faults for coverage of undetected transition faults sites
    Irith Pomeranz (Purdue University)



    Session 2A: Hardware Security
    Room: Grand Hall A
    Time: 14:45-16:25
    Moderator: Sying-Jyan Wang (National Chung Hsing University)
    2A-1: A new active IC metering technique based on locking scan cells
    Aijiao Cui, and Xuesen Qian (Harbin Institute of Technology Shenzhen Graduate School)
    Gang Qu (Maryland University)
    Huawei Li (Chinese Academy of Sciences)
    2A-2: Tree-based logic encryption for resisting SAT attack
    Yung-Chih Chen (Yuan Ze University)
    2A-3: Intra-die-variation-aware side channel analysis for hardware Trojan detection
    Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, and Michiko Inoue (NAIST)
    Alex Orailoglu (UCSD)
    2A-4: On securing scan design from scan-based side-channel attacks
    Satyadev Ahlawat and Darshit Vaghani (Indian Institute of Technology Bombay)
    Jaynarayan T Tudu (Indian Institute of Science)
    Virendra Singh (Indian Institute of Technology Bombay)


    Session 2B: Circuits and Systems Reliability-Enhancement Techniques
    Room: Grand Hall B
    Time: 14:45-16:25
    Moderator: Aijiao Cui (Harbin Institute of Technology Shenzhen Graduate School)
    2B-1: An incremental aging analysis method based on Delta circuit simulation technique
    Si-Rong He, Nguyen Cao Qui, Yu-Hsuan Kuo, and Chien-Nan Liu (National Central University)

    2B-2: Post-silicon test flow for aging prediction
    Hau Hsu, Jing-Jia Liou, Zih-Huan Gao, and Ting-Shuo Hsu (National Tsing Hua University)

    2B-3: Cloud-based PVT monitoring system for IoT devices
    Guan-Hao Lian, Shi-Yu Huang, and Wei-Yi Chen (National Tsing Hua University)
    2B-4: A critical charge model for estimating the SET and SEU sensitivity: a Muller C-element case study
    Marko Andjelkovic, Milos Krstic, and Rolf Kraemer (IHP)
    Varadan Savulimedu Veeravalli and Andreas Steininger (TU Wien)


    Session 2C: Techniques for Testing and Reliability
    Room: Descartes & Rousseau
    Time: 14:45-16:25
    Moderator: Tong-Yu Hsieh (National Sun Yat-sen University)
    2C-1: Design and Implementation of an EG-pool based FPGA formatter with temperature compensation
    Yang-Kai Huang, Kuan-Te Li, Chih-Lung Hsiao, Chia-An Lee, and Jiun-Lang Huang (National Taiwan University)
    Terry Kuo (OpenATE)

    2C-2: SAR TDC architecture with self-calibration employing trigger circuit
    Yuki Ozawa, Takashi Ida, Rishen Jiang, Shotaro Sakurai, Seiya Takegami, and Nobukazu Tsukiji (Gunma University)
    Ryoji Shiota (Socionex)
    Haruo Kobayashi (Gunma University)

    2C-3: Bringing fault-tolerant GigaHertz-computing to space: A Multi-Stage Software-Side Fault-Tolerance Approach for Miniaturized Spacecraft
    Christian M. Fuchs, Todor P. Stefanov, Nadia M. Murillo, and Aske Plaat (Leiden University)

    2C-4: Identification of efficient clustering technique for test power activity on the layout
    Harshad Dhotre, Stephan Eggersglüß, and Rolf Drechsler (University of Bremen)




    November, 29th
    --------------------------------------------------------------------------------------------------------------

    Registration
    Time: 08:00-08:30


    Keynote Session
    Room: Grand Hall
    Time: 08:30-10:10

    Keynote #2: Addressing Automotive Safety Challenge & Solutions
    Presenter: Yervant Zorian (Synopsys)
    Chair: Cheng-Wen Wu (National Tsing-Hua University)
    Keynote #3: Volume Diagnosis
    Presenter: Wu-Tung Cheng (Mentor Graphics)
    Chair: Shi-Yu Huang (National Tsing-Hua University)


    Session 3A: Special Session on Hardware-Oriented Security and Trust
    Room: Grand Hall A
    Time: 10:40-12:20
    Organizer: Huawei Li (Chinese Academy of Sciences)
    Moderator: Huawei Li (Chinese Academy of Sciences)
    3A-1: Securing Infrastructure IP in Today’s SoCs
    Yervant Zorian (Synopsys)
    3A-2: Security Implications of Cyberphysical Flow-based Microfluidic Biochips
    Jack Tang, Ramesh Karri (New York University)
    Mohamed Ibrahim, Krishnendu Chakrabarty (Duke University)
    3A-3: How to Secure Scan design against scan-based side-channel attacks?
    Wei Zhou, Aijiao Cui (Harbin Institute of Technology Shenzhen Graduate School)
    Huawei Li (Chinese Academy of Sciences)
    Gang Qu (University of Maryland College Park)



    Session 3B: Scan Test
    Room: Grand Hall B
    Time: 10:40-12:20
    Moderator: Chien-Mo Li (National Taiwan University)
    3B-1: Structure-oriented test of reconfigurable scan networks
    Dominik Ull, Kochte Michael, and Hans-Joachim Wunderlich (University of Stuttgart)

    3B-2: Compaction of a transparent-scan sequence to reduce the fail data volume for scan chain faults
    Irith Pomeranz (Purdue University)

    3B-3: Architecture for reliable scan-dump in the presence of multiple asynchronous clock domains in FPGA SoCs
    Amitava Majumdar, Balakrishna Jayadev, Da Cheng, and Albert Lin (Xilinx)

    3B-4: Scan chain grouping for mitigating IR-drop-induced test data corruption
    Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, and Seiji Kajihara (Kyushu Institute of Technology)
    Jun Qian (Advanced Micro Devices)


    Session 3C: Advanced Testing Techniques
    Room: Descartes & Rousseau
    Time: 10:40-12:20
    Moderator: Chia-Tso Chao (National Chiao Tung University)
    3C-1: Deterministic path delay measurement using short cycle test pattern
    Kentaro Kato (Tsuruoka College)

    3C-2: Cell-aware ATPG to improve defect coverage for FPGA IPs and next generation Zyng MSPSoCs
    Seetal Potluri, Aaron Mathew, Rambabu Nerukonda, Ismed Hartanto, and Shahin Toutounchi (Xilinx)

    3C-3: Testing clock distribution networks
    Sying-Jyan Wang, Hsiang-Hsueh Chen, and Chin-Hung Lien (National Chung-Hsing University)
    Katherine Shu-Min Li (National Sun Yat-sen University)

    3C-4: Test coverage analysis for designs with timing exceptions
    Kun-Han Tsai (Mentor Graphics)
    Srinivasan Gopalakrishnan (Qualcomm)



    Lunch Break (GSC Hiroshima High School Student Research Poster Presentation)
    Room: Grand Hall
    Time: 12:20-13:30


    Social Event
    Time: 13:30~17:00


    Banquet
    Time: 17:30~21:00




    November, 30th
    -------------------------------------------------------------------------------------------------

    Registration
    Time: 08:00-08:30


    Session 4A: Special Session on Test and Reliability of Emerging Memories
    Room: Grand Hall A
    Time: 08:30-09:45
    Organizer: Said Hamdioui (Delft University of Technology)
    Moderator: Said Hamdioui (Delft University of Technology)
    4A-1: Test and Reliability of STT-MRAMs
    Arijit Raychowdhury (Georgia Institute of Technology)
    4A-2: Test and Reliability of PCMs
    Huawei Li (Chinese Academy of Sciences)
    4A-3: Test and Reliability of RRAMs
    Said Hamdioui (Delft University of Technology)


    Session 4B: Debugging and Design Verification
    Room: Grand Hall B
    Time: 08:30-09:45
    Moderator: Seetal Potluri (Xilinx)
    4B-1: Test and debug strategy for high speed JESD204B Rx PHY
    Surya Piplani, Vivek Mohan Sharma, and Daniele Cervini (STMicroelectronics)
    Humberto Fonseca and David Hardisty (Cadence Design Systems)
    4B-2: Post silicon debugging of electrical bugs using trace buffers
    Kentaro Iwata and Amir Masoud Gharehbaghi (University of Tokyo)
    Mehdi Tahoori (Karlsruhe Institute of Technology)
    Masahiro Fujita (University of Tokyo)
    4B-3: On evaluating and constraining assertions using conflicts in absent scenarios
    Huina Chao, Huawei Li, Xiaoyu Song, Tiancheng Wang, and Xiaowei Li (Chinese Academy of Sciences)


    Session 4C: Yield Enhancement and Diagnosis
    Room: Descartes & Rousseau
    Time: 08:30-09:45
    Moderator: Tomoo Inoue (Hiroshima University)
    4C-1: Yield enhancement by repair circuits for ultra-fine pitch stacked-chip connections
    Keitaro Koga, Hiromitsu Awano, and Makoto Ikeda (University of Tokyo)
    4C-2: Error-tolerability evaluation and test for images in face detection application
    Tong-Yu Hsieh, Tai-Ang Cheng, and Chao-Ru Chen (National Sun Yat-sen University)
    4C-3: PADLOC: physically-aware defect localization and characterization
    Soumya Mittal and Shawn Blanton (Carnegie Mellon)


    Session 5A: Advanced Diagnosis Techniques
    Room: Grand Hall A
    Time: 10:15-11:30
    Moderator: Xinli Gu (Huawei)
    5A-1: Automatic identification of yield limiting layout patterns using root cause deconvolution on volume scan diagnosis data
    Wu-Tung Cheng, Randy Klingenberg, Brady Benware, Wu Yang, Manish Sharma, and Geir Eide (Mentor Graphics)
    Yue Tian and Sudhakar M. Reddy (University of Iowa)
    Yan Pan, Sherwin Fernandes, and Atul Chittora (Global Foundaries)
    5A-2: Scan chain diagnosis based on unsupervised machine learning
    Yu Huang, Brady Benware, Randy Klingenberg, Huaxing Tang, Jayant Dsouza, and Wu-Tung Cheng (Mentor Graphics)

    5A-3: Using cell aware diagnostic patterns to improve diagnosis resolution for cell internal defects
    Huaxing Tang (Mentor Graphics)
    Arvind Jain, Sanil Kumark Pillai, and Dharmesh Joshi (Qualcomm)
    Shamitha Rao (Mentor Graphics)


    Session 5B: Design for Testability
    Room: Grand Hall B
    Time: 10:15-11:30
    Moderator: Masayuki Arai (Nihon University)
    5B-1: Automotive IC on-line test techniques and the application of deterministic ATPG-based runtime test
    Yoichi Maeda, Jun Matsushima (Renesas System Design)
    Ron Press (Mentor Graphics)
    5B-2: Open defect detection with built-in test circuit by IDDT appearance time in CMOS ICs
    Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, and Masaki Hashizume (Tokushima University)
    Shyue-Kung Lu (National Taiwan University of Science and Technology)
    5B-3: Design for testability technique of reversible logic circuits based on exclusive testing
    Joyati Mondal and Debesh Kumar Das (Jadavpur University)


    Session 5C: Memory Test and Reliability
    Room: Descartes & Rousseau
    Time: 10:15-11:30
    Moderator: Masahiro Fujita (University of Tokyo)
    5C-1: Fault-aware page address remapping techniques for enhancing yield and reliability of flash memories
    Shyue-Kung Lu and Shu-Chi Yu (National Taiwan University of Science and Technology)
    Masaki Hashizume (The University of Tokushima)

    5C-2: 3D IC memory BIST controller allocation for test time minimization under power constraints
    Yen-Chun Ko and Shih-Hsu Huang (Chung Yuan Christian University)

    5C-3: A heuristic algorithm for Automatic generation of march tests
    Xiaole Cui, Yichi Luo, and Qiujun Lin (Peking University Shenzhen Graduate School)
    Xiaoxin Cui (Peking University)