Keynotes & Invited Talk
Title: The Revival of BIST: From Self-Test to Self-Healing
Speaker: Prof. Hans-Joachim Wunderlich, University of Stuttgart, DEU
Date: Tuesday, 28 Nov., 2017
Built-in self-test techniques have been around for 50 years. The early approaches were based on random pattern testing for cost minimization and have been improved over the years to reduce test time and increase fault coverage. Despite these efforts, logic BIST has been a niche application for many years due to concerns about hardware area costs, design and validation effort and the impact on timing and the functional behavior.
With the high functional safety requirements in electronic mass markets like automotive, the situation has changed. BIST had to be extended from production and offline test to in-system runtime test. The appearance of multi-core SoCs and many-core processors, made modular and hierarchical approaches a necessity.
As a next step, self-aware systems are found in automotive, industrial, or medical application domains which need to monitor their own state and the capabilities of the underlying hardware platform in addition to monitoring their environment. This comprises for instance timing or voltage margins, error rates and locations, or known faulty components. The knowledge of the hardware fitness is a requirement for qualified adaptation to changing system states and graceful degradation, for instance by voltage or frequency calibration, use of available redundancies, or isolation of known faulty modules.
To capture the state of the hardware platform, a self-aware system integrates instrumentation and sensors to monitor and to examine the state of its hardware structures. The employed instrumentation spans from design-for-test and diagnosis features, fault-tolerant design, and different types of monitors to the required control and access mechanisms that interconnect them.
Today we see the first steps towards hardware standards and functional approaches supporting in-field monitoring and calibration, self-awareness and fault management. The talk will cover the main challenges we have overcome in the past, and the challenges we are facing now in order to apply BIST in critical applications like automotive and medicine.
Hans-Joachim Wunderlich studied Mathematics and Philosophy at the universities of Konstanz and Freiburg, and received his Ph. D. degree in computer science from the University of Karlsruhe, Germany, where he continued as an assistant professor. In 1990, he started working as a full professor at the universities of Duisburg, Siegen and Stuttgart. Since 2002, he has been the head of the Institute of Computer Architecture and Computer Engineering of the University of Stuttgart. His main research interests cover design and test automation of circuits and systems, fault tolerance and dependability as well as test and built-in self-test. He published close to 300 scientific articles in these areas, and he is a Fellow of IEEE.
Hans-Joachim Wunderlich is a full professor and the director of the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart. He studied Mathematics and Philosophy at the Universities of Konstanz and Freiburg, Germany, and received his PhD degree (Dr. rer. nat.) from the University of Karlsruhe in 1986. After this, he has worked as a professor at the universities of Karlsruhe, Duisburg, Siegen and Stuttgart. Since 2002, he has been the head of the Institute of Computer Architecture and Computer Engineering of the University of Stuttgart.
For around 35 years, Prof. Wunderlich contributed to the areas of VLSI testing, Design for Test, Dependability, Fault Tolerance, and Design Automation as well as built-in self-test. He published close to 300 scientific articles in these fields, and led numerous projects funded by industry, European Commission, German government or national funding organizations like DFG. Prof. Wunderlich was recipient of the award for excellent academic teaching of the state of Baden-Württemberg, was promoted Golden Core Member of the IEEE Computer Society, and was elevated Fellow of the IEEE for contributions to very-large-scale-integration circuit testing and fault tolerance.
Title: Addressing Automotive Safety Challenge & Solutions
Speaker: Dr. Yervant Zorian, Synopsys
Date: Wendesday, 29 Nov., 2017
Given today’s fast growing automotive semiconductor industry, this keynote will discuss the trends, challenges and implications of automotive safety requirements on all aspects of the SOC lifecycle: design, silicon bring-up, volume production, and particularly in-system functional safety. Today’s automotive chips need multiple in-system self-test modes, such as power-on self-test and repair, periodic in-field self-test, advanced error correction, etc. This keynote will cover these specific in-system requirements and the benefits of selecting ISO 26262 certified solutions to ensure standardized functional safety, while accelerating time to market for automotive SOCs.
Dr. Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.
Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science.
He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.
Title: volume diagnosis
Speaker: Dr. Wu-Tung Cheng, Mentor Graphics
Date: Wendesday, 29 Nov., 2017
Volume diagnosis with scan test data has being used successfully in identifying silicon manufacture systematic defects. This presentation will discuss the current status and future challenges and opportunities.
Wu-Tung Cheng is a Chief Scientist and Advanced Test Research Director in Mentor Graphics. He is an IEEE fellow since year 2000. He has 160 publications and 59 patents in semiconductor manufacture test and diagnosis area. In 2006, he received ITC best paper award. In 2008, he received ITC honorable mention award. In 2014, he received ATS best paper award. He received his Ph.D. degree in Computer Science from the University of Illinois at Urbana-Champaign in 1985.
Title: A Foundry’s View of Hardware Security
Speaker: Dr. Shih-Lien Lu, TSMC
Date: Tuesday, 28 Nov., 2017
A system is as secure as its weakest link. Current computing systems employ a multiple-layer approach to build a trusted environment. At the bottom of this multi-layer approach is a hardware root of trust which other layers build upon. It is important to assure this root of trust is secure and free from any weakness. Recently there is surge of research topics on hardware security. In this talk we first narrow the topic a bit and outline a tighter definition of hardware security. We, then, focus on a few topics related to this tighter definition of hardware security including hardware Trojans and IC counterfeiting. On hardware Trojans, we first explain why it is so hard to prevent hardware Trojans. While we are at it we will argue why it is very unlikely for a reputable foundry such as TSMC to plant them. On IC counterfeiting, there have been work on employing Physically Unclonable Function (PUF) to prevent counterfeiting. In this talk we will explain the difference between testing of these hardware security elements from testing of standard logic elements. We will also clarify that foundry is in the best position to design and build these elements such as Physical Unclonable Functions (PUFs) and Physical Random Bits Generators (PRBGs). Biography:
Shih-Lien Lu is currently a director at TSMC. From 1999 to 2016 he was with Intel Corporation. While at Intel he was a research scientist, a research group manager and later the Director of Memory Architecture Lab, Intel Labs. He was on the faculty of the ECE Department at the Oregon State University from 1991 to 2001 (on leave the last two years). From 1984 to 1991 he worked on the MOSIS project at USC/ISI which provides research and education community VLSI fabrication services. His research interests include computer architecture, memory system and circuits, VLSI design and hardware security. An IEEE Fellow, Shih-Lien received his BS in EECS from UC Berkeley and MS and PhD both in CSE from UCLA.