Organizing Committee

  • Tutorial I

    Title: Power-Aware Testing in the Era of IoT

    Speaker 1: Prof. Xiaoqing Wen, Kyushu Institute of Technology, Department of CSE

    Speaker 2: Dr. Patrick Girard, LIRMM / CNRS

    Date: Monday, 27 Nov., 2017


    Managing the power consumption of circuits and systems has become one of the most important challenges for the semiconductor industry, especially in the era of IoT. Sophisticated power management techniques, such as voltage scaling, clock gating, power gating, etc., are widely used today to control the power dissipation during the functional operation. Since the application of these techniques has profound implications on manufacturing test, power-aware testing has become indispensable for low-power LSIs and IoT devices. This tutorial provides a comprehensive and practical coverage of power-aware testing, with the following three parts. The first part gives the background and discusses various problems arising from excessive power dissipation during scan testing. The second part provides comprehensive information on structural and algorithmic solutions for alleviating the test-power-related problems. The third part outlines low power design techniques and shows how these low power devices can be tested safely without affecting yield and reliability.


    Speaker 1:

    Xiaoqing WEN received a B.E. degree from Tsinghua University, China, in 1986, a M.E. degree from Hiroshima University, Japan, in 1990, and a Ph.D. degree from Osaka University, Japan, in 1993. From 1993 to 1997, he was an Assistant Professor at Akita University, Japan. He was a Visiting Researcher at University of Wisconsin, Madison, USA, from October 1995 to March 1996. He joined SynTest Technologies, Inc., USA, in 1998, and served as its CTO until 2003. In 2004, he joined Kyushu Institute of Technology, Japan, where he is currently a Professor and the Chair of the Department of Creative Informatics. He co-founded Dependabale Integrated Systems Reserch Center (DISC) in 2015 and servied as its first Director. He is a Co-Chair of the Technical Activity Committee on Power-Aware Testing under the Test Technology Technical Council (TTTC) of the IEEE Computer Society. He is serving as Associate Editors for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration Systems, and Journal of Electroics Testing: Theory and Aplications. He co-authored and co-edited two books: VLSI Test Principles and Architectures: Design for Testability (Morgan Kaufmann, 2006) and Power-Aware Testing and Test Strategies for Low Power Devices (Springer, 2009). His research interests include design, test, and diagnosis of integrated circuits. He holds 43 U.S. Patents and 14 Japan Patents. He received the 2008 Society Best Paper Award from the Infromation Systmes Society (ISS) of Institute of Electronics, Information and Communication Engineers (IEICE). He is a Fellow of IEEE, a Senior Member of Information Processing Society of Japan (IPSJ), and a member IEICE.

    Speaker 2:

    Patrick GIRARD received a M.Sc. degree in Electrical Engineering and a Ph.D. degree in Microelectronics from the University of Montpellier, France, in 1988 and 1992 respectively. He is currently Research Director at CNRS (French National Center for Scientific Research) and works in the Microelectronics Department of the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) - France. From 2010 to 2014, he was head of this Microelectronics Department. He is co-Director of the International Associated Laboratory «LAFISI» (French-Italian Research Laboratory on Hardware-Software Integrated Systems) created in 2013 by the CNRS and the University of Montpellier with the Politecnico di Torino, Italy. His research interests include all aspects of digital testing and memory testing, with emphasis on critical constraints such as timing and power. Reliability and fault tolerance are also part of his research activities. He has served on numerous conference committees and is the founder and Editor-in-Chief of the ASP Journal of Low Power Electronics (JOLPE). He is also an Associate Editor of the IEEE Transactions on Computers, IEEE Transactions on CAD and the Journal of Electronic Testing – Theory and Applications (JETTA - Springer). He has supervised 35 PhD dissertations and has published 6 books or book chapters, 65 journal papers, and more than 230 conference and symposium papers on these fields. Patrick Girard is a Fellow of IEEE.

  • Tutorial II

    Title: Data-Driven Resiliency Solutions for Integrated Circuits and Systems

    Speaker: Prof. Krishnendu Chakrabarty, Department of Electrical and Computer Engineering, Duke University

    Date: Monday, 27 Nov., 2017


    Design-time solutions and guard-bands for resilience are no longer sufficient for integrated circuits and electronic systems. This tutorial will describe how data analytics and real-time monitoring can be used to ensure that integrated circuits, board, and systems operate as intended. The speaker will first present a representative critical path (RCP) selection method based on machine learning and linear algebra that allows us to measure the delay of a small set of paths and infer the delay of a much larger pool of paths. In the second part of the talk, the speaker will focus on the resilience problem for boards and systems; we are seeing a significant gap today between working silicon and a working board/system, which is reflected in failures at the board and system level that cannot be duplicated at the component level. The speaker will describe how machine learning, statistical techniques, and information-theoretic analysis can be used to close the gap between working silicon and a working system. Finally, the presenter will describe how time-series analysis can be used to detect anomalies in complex core router systems.


    Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now the William H. Younger Distinguished Professor of Engineering in the Department of Electrical and Computer Engineering and Professor of Computer Science at Duke University. He also serves as Director of Graduate Studies for Electrical and Computer Engineering (till August 31, 2017). On September 1, 2017, he will start become the Chair of the Electrical and Computer Engineering Department at Duke University. Prof. Chakrabarty is a recipient of the National Science Foundation CAREER award, the Office of Naval Research Young Investigator award, the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Transactions on CAD Donald O. Pederson Best Paper Award (2015), the ACM Transactions on Design Automation of Electronic Systems Best Paper Award (2017), and over a dozen best paper awards at major conferences. He is also a recipient of the IEEE Computer Society Technical Achievement Award (2015), the IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award (2017), and the Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur (2014). He is a Research Ambassador of the University of Bremen (Germany) and a Hans Fischer Senior Fellow (named after Nobel Laureate Prof. Hans Fischer) at the Institute for Advanced Study, Technical University of Munich, Germany. He has held Visiting Professor positions at University of Tokyo and the Nara Institute of Science and Technology (NAIST) in Japan, and Visiting Chair Professor positions at Tsinghua University (Beijing, China) and National Cheng Kung University (Tainan, Taiwan). He is a De Tao Master of Emerging Information Technologies, DeTao Masters Academy of the DeTao Group in China. Prof. Chakrabarty’s current research projects include: testing and design-for-testability of integrated circuits and systems (including SOC and 3D integrated circuits); digital microfluidics, biochips, and cyberphysical systems; data analytics for fault diagnosis, failure prediction, anomaly detection, and hardware security; smart manufacturing. Prof. Chakrabarty is a Fellow of ACM, a Fellow of IEEE, and a Golden Core Member of the IEEE Computer Society. He holds nine US patents, with several patents pending. He was a 2009 Invitational Fellow of the Japan Society for the Promotion of Science (JSPS). He is a recipient of the 2008 Duke University Graduate School Dean’s Award for excellence in mentoring, and the 2010 Capers and Marion McDonald Award for Excellence in Mentoring and Advising, Pratt School of Engineering, Duke University. He has served as a Distinguished Visitor of the IEEE Computer Society (2005-2007, 2010-2012), a Distinguished Lecturer of the IEEE Circuits and Systems Society (2006-2007, 2012-2013), and an ACM Distinguished Speaker (2008-2016). Prof. Chakrabarty served as the Editor-in-Chief of IEEE Design & Test of Computers during 2010-2012 and ACM Journal on Emerging Technologies in Computing Systems during 2010-2015. Currently he serves as the Editor-in-Chief of IEEE Transactions on VLSI Systems. He is also an Associate Editor of IEEE Transactions on Biomedical Circuits and Systems, IEEE Transactions on Multiscale Computing Systems, and ACM Transactions on Design Automation of Electronic Systems.